Archive25 posts

This article demonstrates a functional system on a PYNQ-Z2 FPGA development board that accelerates a 2-D convolution operation by impelemnting it in programmable logic.

The articles talks about everything you need to know about getting that dream job as an FPGA designer at a HFT firm.

A quick reference to the different elements of PCB designing in altimum designer

This page has all the information, instructions and demos related to accessing the Pynq-Z2 FPGA development board.

Metastability and mean time between failure are two very common terms you will hear in the context of digital logic and RTL design. This article collects an exhaustive set of concepts and resources to understand these ideas

With chiprentals, students and developers of digital design can get access to FPGA Development boards over the internet along with a fully set up host system to program and play around.

In this article I have documented a conversation I had during an interview where I had to apply all my knowledge of CDC in one go.

This quick guide gives you a simple plug and play setup of all the latest open source EDA tools that enable you to design, simulate and test your RTL on any operating system, including ios.

This is the only resource you need to refer to in order to feel confident about your next RTL design interview.

This article talks about the issue of convergnece and divergence in designs with multiple clock domain crossings.

This tutorial is a one stop solution for everything you will ever need to learn about clock domain crossing. The best resources from across the internet have been curated here

This series of articles consists of discussion about resources that can teach you way more than your college lectures and give you practical skills that are actually employable.

This article tries to demystify the field of digital logic design for those unacquainted with its complexities and differences in the though process when compared to the traditional world of programming.

In this tutorial, we look at cocotb, an upcoming popular verification framework that let's you control signals directly from python!

In this article, we look at a quick way to automate your testbenches and find bugs in your code.

In this article, we put all the modules that we've designed in this series together and build a single unit of a CNN architecture.

This comprehensive guide aims to guide you in your search for the perfect FPGA development board.

An article showing beginners how they can generate a global reset signal at the initialization of the design without having to sacrifice a GPIO pin or a user button for the same

In this article we convert normal additions and multiplications in our design to fixed point representations. This will enable use to work with fractional numbers.

In this article we implement some common activation functions used in machine learning algorithms. This is a part of the series where we design a Convolutional Neural Network accelerator targeted towards FPGAs

In this article we design a module that can very efficiently perform Max Pooling and Average pooling of an input matrix in Verilog HDL. This will go into our Deep Learning accelerator as mentioned in the previous articles in the series.

There has been a lot of interest in the tech community lately to accelerate data intensive artificial intelligence inference operations. This series of articles goes into a great detail in implementing an FPGA based AI accelerator in Verilog HDL.

In this article, we design a fully parameterized 2D convolution engine in Verilog HDL and verify its functionality with a golden model written in python.

There has been a lot of interest in the tech community lately to accelerate data intensive machine learning inference operations. This series of articles goes into a great detail in implementing an FPGA based accelerator in verilog HDL.

A Shift registers is a very common design element in any digital design. This will be the only shift register you will ever need to write. The parameters in this code can be modified to create a shift register of any size and bit-width.