Putting it all together: The CNN accelerator
In this article, we put all the modules that we've designed in this series together and build a single unit of a CNN architecture.
Machine Learning6 posts
The Activation Function
In this article we implement some common activation functions used in machine learning algorithms. This is a part of the series where we design a Convolutional Neural Network accelerator targeted towards FPGAs
The Pooling Unit
In this article we design a module that can very efficiently perform Max Pooling and Average pooling of an input matrix in Verilog HDL. This will go into our Deep Learning accelerator as mentioned in the previous articles in the series.
FPGA based acceleration of machine learning algorithms involving convolutional neural networks
There has been a lot of interest in the tech community lately to accelerate data intensive machine learning inference operations. This series of articles goes into a great detail in implementing an FPGA based accelerator in verilog HDL.
Architecture Outline : Machine Learning Accelerator
There has been a lot of interest in the tech community lately to accelerate data intensive artificial intelligence inference operations. This series of articles goes into a great detail in implementing an FPGA based AI accelerator in Verilog HDL.
The convolution Engine
In this article, we design a fully parameterized 2D convolution engine in Verilog HDL and verify its functionality with a golden model written in python.