Blog

Technical articles on FPGA design, RTL, verification, and industry-shaped learning paths.

Series

CNN Accelerator

Build an FPGA-based ML accelerator from convolution engine to full system integration.

• FPGA based acceleration of machine learning algorithms involving convolutional neural networks
• Architecture Outline : Machine Learning Accelerator
• The convolution Engine
• The Activation Function
• The Pooling Unit
• Adding Fixed point arithmetic to your design
• Putting it all together: The CNN accelerator
• Accelerating a 2-D image convolution operation on FPGA Hardware

Interview prep

Concepts and Interview Prep

CDC, metastability, and interview-grade RTL topics for FPGA and HFT roles.

• The Complete Guide to Preparing for a High-Frequency Trading FPGA Developer Interview
• Preparing for an RTL Design Interview: An Exhaustive List of Topics
• Clock domain crossing (CDC) - The complete reference guide
• The Best Interview Question on Clock Domain Crossing
• What is Metastability and MTBF in the context of clock domain crossing
• Convergence and Divergence in CDC and why it's a problem

Minis

Minis

Short, practical notes you can apply the same day.

• How to reset your FPGA design at start up without using an external pin or button
• How to write a parameterized universal shift register in verilog

Tools

Tools and guides

Dev boards, verification, HLS, and tooling setup for FPGA and ASIC work.

• How to choose an FPGA dev board in 2020. A comprehensive guide
• A gentle introduction to CocoTb
• Creating automated testbenches for your digital designs using python and iverilog
• The quick and complete tool setup for FPGA and ASIC design
• PCB design in altium
• A gentle introduction to digital logic design for software developers via HLS
• Instructions for accessing chiprentals PYNQ-Z2 hardware
• Introducing Chiprentals, an FPGA renting platform