Courses
Hands-on RTL design problems
Problems inspired by real silicon with long-form video solutions on QuickSilicon covering microarchitecture, tradeoffs, and rationale.
Live courses
Live
Hands-On RTL design for Networking Systems
As part 1 of the set of courses on HFT accelerator design this is a set of handpicked design problems inspired by real world silicon designs. This problemset has a special focus in designs from the world of networking systems.
Covers various sub-topics ranging from simple gearboxes to complex packet parsers, arbiters and timing logic. Power, performance and area tradeoffs to be handled in each problem.
Use code QS-THEDATABUS for a 10% discount.
Upcoming courses
Under Construction
Hands-On HFT Design
This will be a project based course where we will solve multiple problems with the aim of implementing a full functional system that is capable of processing data meant for HFT applications and taking actions like one. This will include functions like decoding of market data packets for specific exchange protocols, doing math on the data to take decisions and triggering order packets based on the result.
There will be a high focus on building low latency modules for achieving the above purposes. The course will build upon concepts introduced in the Hands-On RTL Design for Networking Systems course.
Ideal for someone looking to get a taste of building cutting edge trading infrastructure.
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Why I made this
Back when I was a student of digital design, one of the most frustrating aspects of this field was that most things were built behind closed doors. With work happening inside corporate entities that gatekeep their designs and have no incentive to share it with the wider world, being a student simply meant a lack of access to quality resources.
Truth be told, that remains true to this day. Especially when we compare this with the world of software, students of electrical engineering in general have much less access to quality content that mirrors designs in the real world silicon designs where tradeoffs between power, performance, area, timing, schedule, budget and many more things pull and push design decisions in different directions.
This was one of the key motivators for me to create this site. The overwhelmingly positive response I receive from the consumers is validation to the fact that quality resources are badly needed in this community.
We also lack ecosystems similar to leetcode, Huggingface and Kaggle that students from the world of software enjoy. There's HDLbits, you might say but I believe HDLbits misses one of the key aspects of this job. Most of the work done by an FPGA or ASIC designer happens on whiteboards, sheets of paper, excel documents and block diagrams. It happens in the minds of the designers constantly brainstorming about how to handle the tradeoffs and make the design better. Once all of these are in place, actually writing the RTL becomes a rather straight forward and mechanical (although important) task. Some wise and experienced people I've met in this industry use the rather menial term 'design entry' for the process of actually writing the RTL. So a simple leetcode type interface that HDLbits gives you does not do full justice to the rich and variety filled job of being a designer.
When served in the current format on Quicksilicon, I was able to attack most of these problems. I'm able to go beyond simple RTL drills and actually talk about the design pattern under discussion, how it shows up in the real industry and then spend enough time motivating the microarchitecture and other tradeoffs around that pattern before I show the RTL solution. Running other steps like lint, sythesis and performance testing are also done in this format along with providing a discussion platform on Discord for students to connect with me and others in the community.