Adding Fixed point arithmetic to your design
In this article we convert normal additions and multiplications in our design to fixed point representations. This will enable use to work with fractional numbers.
In this article we convert normal additions and multiplications in our design to fixed point representations. This will enable use to work with fractional numbers.
In this article we design a module that can very efficiently perform Max Pooling and Average pooling of an input matrix in Verilog HDL. This will go into our Deep Learning accelerator as mentioned in the previous articles in the series.
